Modernize Chip Solutions

Minimum 15+ Years of experience SoC Physical Design.Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm.Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must.This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Minimum 15+ Years of experience SoC Physical Design. Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Experience: 5+ yearsLocation: BangaloreBack end STA with skills on Innovas 3, 5, 7 nm, Prime time Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)Will need to be hands-on, defining...

Experience: 5+ years Location: Bangalore Back end STA with skills on Innovas 3, 5, 7 nm, Prime time Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....) Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis) Will need to be hands-on, defining...

Experience in USB HOST side driver dev - CSI/DSI in ON semi 's camera stack controller.· Experience in Driver development side like ESGA drivers 3.X- HAL level· Experience in OS like Zephyr (would be a plus) or any other OS is good.· Person who can write the testcases ARM M55/ security processor in either Python/C.· Core Management in Battery saver·...

Experience in USB HOST side driver dev - CSI/DSI in ON semi 's camera stack controller. · Experience in Driver development side like ESGA drivers 3.X- HAL level · Experience in OS like Zephyr (would be a plus) or any other OS is good. · Person who can write the testcases ARM M55/ security processor in either Python/C. · Core Management in Battery...

Candidate will be responsible for developing test artifacts for production ready software following a defined software development process. The candidate(s) must be capable of analysing specifications, developing test plans, test cases and verifying functionality.- Responsible for all levels of software testing (System, Integration, and Regression)-...

Candidate will be responsible for developing test artifacts for production ready software following a defined software development process. The candidate(s) must be capable of analysing specifications, developing test plans, test cases and verifying functionality.Responsible for all levels of software testing (System, Integration, and Regression)Knowledge on...

Candidate will be responsible for developing test artifacts for production ready software following a defined software development process. The candidate(s) must be capable of analysing specifications, developing test plans, test cases and verifying functionality. Responsible for all levels of software testing (System, Integration, and Regression)...

Candidate will be responsible for developing test artifacts for production ready software following a defined software development process. The candidate(s) must be capable of analysing specifications, developing test plans, test cases and verifying functionality. Responsible for all levels of software testing (System, Integration, and Regression)...

Candidate will be responsible for developing test artifacts for production ready software following a defined software development process. The candidate(s) must be capable of analysing specifications, developing test plans, test cases and verifying functionality. Responsible for all levels of software testing (System, Integration, and Regression)Knowledge...

Responsibilities include, but not limited to:- Deep understanding of SoC for top-down/bottom-up physical design integration in 7nm and lower technologies- Proficient in package co-design concepts • Drive Sub-block/partition decisions, floorplan for the best PPAS- Generate sub-block/partition interface budgets, review- Must have deep functional knowledge of...

Experience: 4+ yearsLocation: BangaloreBack end STA with skills on Innovas3, 5, 7 nm, Prime time- Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)- Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)- Will need to be hands-on, defining...

Experience: 8+ years Location: Bangalore Back end STA with skills on Innovus 3, 5, 7 nm, Prime time

Experience: 4+ yearsLocation: BangaloreBack end STA with skills on Innovas3, 5, 7 nm, Prime timeExperience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)Will need to be hands-on, defining...

Responsibilities include, but not limited to:Deep understanding of SoC for top-down/bottom-up physical design integration in 7nm and lower technologiesProficient in package co-design concepts • Drive Sub-block/partition decisions, floorplan for the best PPASGenerate sub-block/partition interface budgets, reviewMust have deep functional knowledge of P&R...

Analog and Reliability validationExperience -> 3 t o5 yrsLocation - BangaloreJD:The individual would work in the Design Enablement team for Analog IP validation.This includes functional, structural and reliability (aging) validation of Analog IPs in the context of integration testing with various other IPs to be used for SoC building.Skills: 3-4 year...

Experience: 3+ yearsLocation: Bangalore- 3+ years of AMS design verification experience.- Fluent in System Verilog and real number modeling.

Experience: 8+ yearsLocation: BangaloreBack end STA with skills on Innovus3, 5, 7 nm, Prime time

Experience: 8+ years Location: Bangalore Back end STA with skills on Innovus 3, 5, 7 nm, Prime time