Modernize Chip Solutions

Minimum 15+ Years of experience SoC Physical Design.Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm.Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must.This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Analog and Reliability validationExperience -> 3 t o5 yrsLocation - BangaloreJD:The individual would work in the Design Enablement team for Analog IP validation. This includes functional, structural and reliability (aging) validation of Analog IPs in the context of integration testing with various other IPs to be used for SoC building. Skills: 3-4 year...

Experience: 4+ yearsLocation: BangaloreBack end STA with skills on Innovas3, 5, 7 nm, Prime timeExperience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)Will need to be hands-on, defining...

Experience in USB HOST side driver dev - CSI/DSI in ON semi 's camera stack controller.· Experience in Driver development side like ESGA drivers 3.X- HAL level· Experience in OS like Zephyr (would be a plus) or any other OS is good.· Person who can write the testcases ARM M55/ security processor in either Python/C.· Core Management in Battery saver·...

Candidate will be responsible for developing test artifacts for production ready software following a defined software development process. The candidate(s) must be capable of analysing specifications, developing test plans, test cases and verifying functionality. Responsible for all levels of software testing (System, Integration, and Regression)...

Design Verification : 4 to 12 yearsProficiency in System VerilogDefine products test plans & cases from scratchProficiency in UVM methodologyExtensive experience in building digital verification frameworks from scratch, using UVMmethodologyProficiency in System Verilog AssertionsMust be able and willing to investigate in detail the designed product and...

Responsibilities include, but not limited to:Deep understanding of SoC for top-down/bottom-up physical design integration in 7nm and lower technologiesProficient in package co-design concepts • Drive Sub-block/partition decisions, floorplan for the best PPASGenerate sub-block/partition interface budgets, reviewMust have deep functional knowledge of P&R...

Responsibilities include, but not limited to: Deep understanding of SoC for top-down/bottom-up physical design integration in 7nm and lower technologies Proficient in package co-design concepts • Drive Sub-block/partition decisions, floorplan for the best PPAS Generate sub-block/partition interface budgets, review Must have deep functional knowledge of P&R...

BE/BTech/ME in Computers/ Electronics and communications disciplineShould be very strong in C4-8 years of experience in Firmware/ driver development (SPI, MDIO, UART etc)Having strong experience in Ethernet, TCP/IP Networking based products.Should have worked on RTOS based environment and should be good at debuggingProficient in test automation and scripting...

PD methodology and library validation Role: The individual would work in Design Enablement team for Physical Design flow and library validation. This includes RTL to GDS2 integration validation of test blocks implemented with different std cell architectures, macros and across different technologies. Sign-off flow validation like STA, DRC, LVS, PEX will be...

Minimum 15+ Years of experience So C Physical Design. Skills – have working experience in advanced Fin FET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys Pn R/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin...

Minimum 15+ Years of experience SoC Physical Design. Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin...

Minimum 15+ Years of experience SoC Physical Design.Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm.Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must.This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Minimum 15+ Years of experience SoC Physical Design. Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...

Candidate will be responsible for developing test artifacts for production ready software following a defined software development process. The candidate(s) must be capable of analysing specifications, developing test plans, test cases and verifying functionality. Responsible for all levels of software testing (System, Integration, and Regression) ...

PD methodology and library validation Role: The individual would work in Design Enablement team for Physical Design flow and library validation. This includes RTL to GDS2 integration validation of test blocks implemented with different std cell architectures, macros and across different technologies. Sign-off flow validation like STA, DRC, LVS, PEX...

Responsibilities include, but not limited to: Deep understanding of So C for top-down/bottom-up physical design integration in 7nm and lower technologies Proficient in package co-design concepts • Drive Sub-block/partition decisions, floorplan for the best PPAS Generate sub-block/partition interface budgets, review Must have deep functional...

Experience in USB HOST side driver dev - CSI/DSI in ON semi 's camera stack controller. · Experience in Driver development side like ESGA drivers 3. X- HAL level · Experience in OS like Zephyr (would be a plus) or any other OS is good. · Person who can write the testcases ARM M55/ security processor in either Python/C. · Core Management in...

Experience: 4+ years Location: Bangalore Back end STA with skills on Innovas 3, 5, 7 nm, Prime time Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....) Complex high-speed designs for edge computing applications (3.2 G HBM PHY, Processor hardening for PPA analysis) Will need to be...

Analog and Reliability validation Experience - 3 t o5 yrs Location - Bangalore JD: The individual would work in the Design Enablement team for Analog IP validation. This includes functional, structural and reliability (aging) validation of Analog IPs in the context of integration testing with various other IPs to be used for So C building. ...