Memory Layout Engineer

Job Description: Memory Layout EngineerExperience - 2+ yearsWe are seeking a highly skilled and experienced Memory Layout Engineer to join our team. The ideal candidate will have hands-on expertise in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. You will play a critical role in developing and...

ACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to karthick.v@acldigital.com

Hello All, We are looking for Memory Layout 3-5 years of experience in Memory layout. Tech nodes: tsmc 3nm, 5nm. Note: Notice period: Immediate to 30 Days Interested Share the cv: call or Whats App: 9305570731

Hello All,We are looking for Memory Layout 3-5 years of experience in Memory layout.Tech nodes: tsmc 3nm, 5nm .Note: Notice period: Immediate to 30 DaysInterested Share the cv: preeti.rajput@techmahindra.comcall or WhatsApp: 9305570731

Memory LayoutHands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning...

ACL Digital is looking for a 1.Memory Layout Engineer with 2+ years of Exp for Noida 2.Memory Design Engineer with 2+ years of Exp for Noida Interested share cv to

ACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to karthick.v@acldigital.com

Hello All,We are looking for Memory Layout 3-5 years of experience in Memory layout.Tech nodes: tsmc 3nm, 5nm .Note: Notice period: Immediate to 30 DaysInterested Share the cv: preeti.rajput@techmahindra.comcall or WhatsApp: 9305570731

Hello All, We are looking for Memory Layout 3-5 years of experience in Memory layout. Tech nodes: tsmc 3nm, 5nm . Note: Notice period: Immediate to 30 Days Interested Share the cv: call or WhatsApp: 9305570731

5+ years of experience in Memory/Custom Layout design. Memory Leaf cell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC...

Job Title: Senior Memory Design Engineer – Full Custom (8+ Years Experience)We are seeking a highly skilled Senior Memory Design Engineer with 8+ years of hands-on experience in full custom memory design and architectures. The ideal candidate should have expertise in:- SRAM design verification at the compiler level (beyond instance-level verification).-...

Hello All, We are looking for Analog & Memory Layout Engineer Analog layout: 3+ years of experience in Analog layout. Should have experience in higher nodes like 55nm,65nm,90nm etc. should worked on LDO, BGR , ADC/DAC, Comparators and IO blocks. Should have experience in lower nodes like tsmc2nm, 3nm, 5nm. Strong background in basics of analog...

5+ years of experience in Memory/Custom Layout design.Memory Leaf cell layout library design from scratch including top level integration.Good knowledge on different types of memory architectures.Good knowledge in optimized layout design for better performance.Sound knowledge & hands on experience in Finfet technology, layout design and DRC...

Job Title: Senior Memory Design Engineer – Full Custom (8+ Years Experience)We are seeking a highly skilled Senior Memory Design Engineer with 8+ years of hands-on experience in full custom memory design and architectures. The ideal candidate should have expertise in:SRAM design verification at the compiler level (beyond instance-level...

Role: Layout Design of SRAM/CAM/RF custom/compiler memories in 5FF/3FF technologies.Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. level integration, final verification of...

Role: Layout Design of SRAM/CAM/RF custom/compiler memories in 5FF/3FF technologies. Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. level integration, final...

5+ years of experience in Memory/Custom Layout design. Memory Leaf cell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations....

Memory Circuit Designer Exp -5+ Transistor level circuit design on custom SRAM array Margin and corner analysis SPICE or Fast SPICE simulations EMIR Functional verification – schematic vs. Verilog Cell timing and power characterization Collateral generation such as LIB, LEF, CMM, OAS Memory Mask Layout Designer Exp – 5+ Mask layout...

Memory Circuit Designer Exp -5+ Transistor level circuit design on custom SRAM array Margin and corner analysis SPICE or FastSPICE simulations EMIR Functional verification – schematic vs. Verilog Cell timing and power characterization Collateral generation such as LIB, LEF, CMM, OAS Memory Mask Layout Designer Exp – 5+ Mask layout design on custom SRAM...

Memory Circuit Designer Exp -5+ Transistor level circuit design on custom SRAM array Margin and corner analysis SPICE or FastSPICE simulations EMIR Functional verification – schematic vs. Verilog Cell timing and power characterization Collateral generation such as LIB, LEF, CMM, OAS Memory Mask Layout Designer Exp – 5+ Mask layout...