UST | Senior Memory Design Engineer

Job Description: Memory Layout EngineerExperience - 2+ yearsWe are seeking a highly skilled and experienced Memory Layout Engineer to join our team. The ideal candidate will have hands-on expertise in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. You will play a critical role in developing and...

Memory LayoutHands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning...

JD for DDR Memory validation engineer: Education: BE in Electronic and communications Experience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs) Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance. This is a Work from...

JD for DDR Memory validation engineer: Education: BE in Electronic and communications Experience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs) Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance. This is a Work from...

JD for DDR Memory validation engineer:Education: BE in Electronic and communicationsExperience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs)Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance.This is a Work from...

Job Description: Memory Layout Engineer Experience - 2+ years We are seeking a highly skilled and experienced Memory Layout Engineer to join our team. The ideal candidate will have hands-on expertise in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. You will play a critical role in developing...

Memory Characterization Engineer Here is the JD. Required Skills and Experience: 4+ years of experience in product characterization with emphasis on digital and mixed-signal circuits Expertise in electrical characterization and/or compliance of memory interfaces (DDR5/4/etc., LPDDR5/4/etc.) Expertise in characterization of So C, processors, PLL,...

Memory Characterization EngineerHere is the JD.Required Skills and Experience:4+ years of experience in product characterization with emphasis on digital and mixed-signal circuitsExpertise in electrical characterization and/or compliance of memory interfaces (DDR5/4/etc., LPDDR5/4/etc.)Expertise in characterization of SoC, processors, PLL, Oscillators,...

About UST...UST is a global digital transformation solutions provider. For more than 25 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people, and led by purpose.Exp – 7+ Years Location – Bangalore Working Model – WFO Position – Full Stack...

Memory Layout Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning...

JD for DDR Memory validation engineer:Education: BE in Electronic and communicationsExperience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs)Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance.This is a Work from...

Job Description: IO Layout EngineerCompany Overview:UST Global is a leading digital technology solutions company dedicated to transforming businesses through innovation. With a presence in over 25 countries, we provide cutting-edge solutions in areas such as digital consulting, automation, product engineering, and cloud computing. Our mission is to deliver...

Job Description: IO Layout Engineer Company Overview: UST Global is a leading digital technology solutions company dedicated to transforming businesses through innovation. With a presence in over 25 countries, we provide cutting-edge solutions in areas such as digital consulting, automation, product engineering, and cloud computing. Our mission is to...

Memory Characterization Engineer Here is the JD. Required Skills and Experience:4+ years of experience in product characterization with emphasis on digital and mixed-signal circuits Expertise in electrical characterization and/or compliance of memory interfaces (DDR5/4/etc., LPDDR5/4/etc.)Expertise in characterization of So C, processors, PLL, Oscillators,...

Memory Characterization Engineer Here is the JD. Required Skills and Experience: 4+ years of experience in product characterization with emphasis on digital and mixed-signal circuits Expertise in electrical characterization and/or compliance of memory interfaces (DDR5/4/etc., LPDDR5/4/etc.) Expertise in characterization of SoC, processors, PLL,...

Memory Characterization EngineerHere is the JD.Required Skills and Experience:4+ years of experience in product characterization with emphasis on digital and mixed-signal circuitsExpertise in electrical characterization and/or compliance of memory interfaces (DDR5/4/etc., LPDDR5/4/etc.)Expertise in characterization of SoC, processors, PLL, Oscillators,...

Memory Characterization Engineer Here is the JD. Required Skills and Experience: 4+ years of experience in product characterization with emphasis on digital and mixed-signal circuits Expertise in electrical characterization and/or compliance of memory interfaces (DDR5/4/etc., LPDDR5/4/etc.) Expertise in characterization of SoC, processors, PLL,...

Position: Senior Memory Design EngineerLocation: Bangalore / NoidaResponsibilities:As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.Required Skills and Experience :Understanding of computer architecture and concepts.Basic understanding of CMOS...

JD for DDR Memory validation engineer:Education: BE in Electronic and communicationsExperience: 5-7 years exp in Post Si validation and System engineering lab (last 3 years in Memory) (prefer exp in AMD labs)Need: Immediate joiner only profiles needed; No of positions :1; Duration 6 months, scope of increase based on performance.This is a Work from...

Job Description: IO Layout Engineer Company Overview: UST Global is a leading digital technology solutions company dedicated to transforming businesses through innovation. With a presence in over 25 countries, we provide cutting-edge solutions in areas such as digital consulting, automation, product engineering, and cloud computing. Our mission is to...