Digital design leader

RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e. G., RV32/64/128, Privileged Architecture, Custom Extensions). Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using System Verilog, UVM (Universal Verification Methodology), and...

&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding...

PCIe Verification: Lead the verification of PCIe (PCI Express) interface designs, ensuring compliance with PCIe protocol standards (e.G., PCIe Gen 3/4/5/6, USB3, etc.). Testbench Development: Develop and implement scalable, reusable, and efficient testbenches for PCIe designs using SystemVerilog, UVM (Universal Verification Methodology), and other...

Hi Folks ACL Digital is Hiring!Experience: 4 - 5+ Years Location: Bangalore / Hyderabad Looking: Immediate to 20 days Hiring | RTL Design Engineer Strong experience in RTL Design using Verilog/System Verilog Exposure to complex So C/ASIC design and integration Hands-on with synthesis, Lint, CDC preferred Share resume at Thanks, K Himabindu

SOC RTL Design Verification Experience : 4 to 10 Years Development and verification of post-si validation sequences using C/C++• Experienced with Verilog, System Verilog, and C or C++• Candidate past experience requirements, • Should have experience in system-level Verification. • DDR prior experience is not mandatory. ACL Digital, a leader in...

PCIe Verification: Lead the verification of PCIe (PCI Express) interface designs, ensuring compliance with PCIe protocol standards (e. G., PCIe Gen 3/4/5/6, USB3, etc.). Testbench Development: Develop and implement scalable, reusable, and efficient testbenches for PCIe designs using System Verilog, UVM (Universal Verification Methodology), and other...

Senior Design Verification Engineer Location: Bangalore. Experience: 4 to 10 Years. Notice Period: Any. Perform verification of complex digital designs at block and system level. Develop testbenches using SystemVerilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve coverage targets using...

Location: Mumbai / Pune / Remote Experience: 15+ Years Function: Digital Marketing Solutioning & PresalesAbout eClerxeClerx is a leading provider of business process management, data-driven solutions, and digital transformation services for global Fortune 500 clients. We combine deep domain expertise with cutting-edge technology to deliver impactful,...

Senior Design Verification Engineer Location: Bangalore. Experience: 4 to 10 Years. Notice Period: Any. Perform verification of complex digital designs at block and system level. Develop testbenches using System Verilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve coverage targets...

Senior Design Verification Engineer Location: Bangalore. Experience: 4 to 10 Years. Notice Period: Any. Perform verification of complex digital designs at block and system level. Develop testbenches using System Verilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve...