Digital design leader

4 weeks ago


Bangalore, India ACL Digital Full time

RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e. G., RV32/64/128, Privileged Architecture, Custom Extensions). Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using System Verilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies. Instruction Set Architecture (ISA) Compliance: Verify that the RISC-V cores and components comply with the RISC-V ISA and its extensions (e. G., M, A, F, D, C). Ensure correct execution of instructions, exception handling, and interrupt processing. Functional Coverage: Ensure complete functional coverage of all RISC-V operations, corner cases, and compliance with architectural requirements. Verification Plan Creation: Develop detailed verification plans and strategies based on RISC-V specifications, ensuring comprehensive validation of all design features and functional requirements.



  • Bangalore, India ACL Digital Full time

    &## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding...


  • Bangalore, India ACL Digital Full time

    PCIe Verification: Lead the verification of PCIe (PCI Express) interface designs, ensuring compliance with PCIe protocol standards (e.G., PCIe Gen 3/4/5/6, USB3, etc.). Testbench Development: Develop and implement scalable, reusable, and efficient testbenches for PCIe designs using SystemVerilog, UVM (Universal Verification Methodology), and other...


  • Bangalore, India ACL Digital Full time

    SOC RTL Design Verification Experience : 4 to 10 Years Development and verification of post-si validation sequences using C/C++• Experienced with Verilog, System Verilog, and C or C++• Candidate past experience requirements, • Should have experience in system-level Verification. • DDR prior experience is not mandatory. ACL Digital, a leader in...


  • bangalore, India ACL Digital Full time

    About the job Company Description ACL Digital is a leader in offering design-led Digital Experience, Product Innovation, Solutions, and Consulting services. The company helps accelerate innovation and transform businesses from strategy through design, implementation, and management, keeping customer journeys and design at the core. ACL Digital is committed...


  • Bangalore, India ACL Digital Full time

    Senior Design Verification Engineer Experience: 4 to 10 Years. Perform verification of complex digital designs at block and system level. Work closely with RTL design and architecture teams to identify issues. Experience with scripting languages like Python, Perl, or Tcl. Bachelor’s or Master’s degree in Electronics, Electrical, or related field. ACL...


  • bangalore, India ACL Digital Full time

    About the jobCompany DescriptionACL Digital is a leader in offering design-led Digital Experience, Product Innovation, Solutions, and Consulting services. The company helps accelerate innovation and transform businesses from strategy through design, implementation, and management, keeping customer journeys and design at the core. ACL Digital is committed to...


  • Bangalore, India ACL Digital Full time

    Senior Design Verification Engineer Location: Bangalore. Experience: 4 to 10 Years. Notice Period: Any. Perform verification of complex digital designs at block and system level. Develop testbenches using SystemVerilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve coverage targets using...


  • Bangalore, India ACL Digital Full time

    &## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ; &## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;&## ;: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding...


  • Bangalore, India ACL Digital Full time

    ACL Digital is looking for "Senior Design Verification Engineers"Immediate to 30 days Experience of working in complex test-bench/model in Verilog, System Verilog or System C. Experience of working on Functional Verification, So C Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language...


  • bangalore, India ACL Digital Full time

    𝗟𝗲𝗮𝗱 𝗠𝗲𝗺𝗼𝗿𝘆 𝗗𝗲𝘀𝗶𝗴𝗻 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗥𝗲𝘀𝗽𝗼𝗻𝘀𝗶𝗯𝗶𝗹𝗶𝘁𝗶𝗲𝘀: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.𝗥𝗲𝗾𝘂𝗶𝗿𝗲𝗱...