PDK Engineer
3 days ago
PDK_Physical_Verification engineer
Job Purpose: Integrate , enhance , maintain and deploy foundry Physical Verification decks (DRC/LVS/Extraction) for internal Analog and Digital design teams and provide support for the same.
Develop, deploy, maintain and support new physical verification flows across mature and advanced technology nodes
Principal Accountabilities: Adapt, update, enhance, QA and release foundry DRC/LVS/ Parasitic Extraction/PERC rundecks
Develop and run QA Test cases for DRC/LVS and other PV flows.
Provide support to internal customers (Analog Design teams & Digital P&R design teams) on DRC/LVS and Parasitic extraction
Knowledge, Skills and Experience:
6+ years of DRC/LVS development and support experience required. Exceptions made for the right candidates.
Good knowledge of CMOS fundamentals with background in electrical engineering or semiconductor physics
Good basic understanding of DRC, LVS and Parasitic Extraction ,
Knowledge of Calibre SVRF required. PVS/Pegasus experience is a plus
Knowledge of Tcl required. Perl, Python experience desired.
Strong debugging capability, not limited only by Physical verification flows.
Knowledge/Understanding FILL methodology
Knowledge/Understanding Parasitic effects in ICs (Integrated Circuits)
Experience in Calibre PERC applications, e.g., P2P/CD is a plus
Experience in any commercial flow for RDSON, EMIR is beneficial
Familiarity on Cadence custom IC Virtuoso platform, Virtuoso-L and Virtuoso-XL, schematic capture, and layout concepts.
Willingness to gain knowledge and familiarity with several CAD tools
Comfortable, confident working in a fast-paced environment.
Ability to prioritize work and meet deadlines
Good interpersonal and communication skills
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