Senior Physical Design Engineer

Technical RequirementsExcellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.In-depth knowledge of floor planning, power planning, PNR and signoff checksStrong experience in static timing analysis (STA), timing closure, and signal integrity.Expertise in power optimization...

Experience: 3 - 6 YearsNotice period: ImmediateLocation: Bangalore & HyderabadResponsibilitiesMandatory Experience in Full Chip Timing.Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization.Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing...

Director- Physical DesignAbout SemifiveFounded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions....

Should be able to handle Full chip hashtagAdded advantage for #Innovus with Minimum 4 years #PnR (timing/congestion/CTS issues), understanding of hashtag#IO ring,#package support, multi hashtag#voltage design.Deep understanding of the concepts related to hashtag#synthesis, place & route, hashtag#CTS, timing convergence, IR/EM checks and signoff DRC/LVS...

Proxelera is India’s premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post silicon work. We...

PHYSICAL DESIGN ENGINEER/LEAD - NOIDA/Ahmedabad/Bangalore/Hyderabad/Pune(NO WORK FROM HOME OR REMOTE WORK) Job description: 4 to 15 Years of Hands on ExperienceBlock level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,Block level Physical Signoff,Block level Timing Signoff and ECO generation.Block level Power signoff.Good skill on...

Lead and mentor a team of RTL design engineers across multiple SoC projects.Own the design execution from specification to RTL handoff, ensuring functionality, quality, and schedule adherence.Define and implement RTL design methodologies, coding guidelines, and best practices for consistency and reuse.Collaborate with architecture, verification, DFT, and...

Company DescriptionDesign Milieu is a progressive firm specializing exclusively in the field of Landscape Architecture. Established in March 2000, we have successfully handled a diverse range of projects varying in scope from small residential spaces to large ecological sites such as dam environments. Our expertise lies in creating sustainable and innovative...

Greetings from TCS !!!Role : Data EngineerExperience Range : 3-9 YearsLocation of Requirement : PAN IndiaJob Description :4+ years of experience in data engineering or data analytics roles3+ year of experience with Palantir FoundryJob OverviewWe are seeking a Senior Palantir Foundry Developer to join our data engineering and analytics team. In this role, you...

SoC/SS Lead Engineers : Experience in development of UVM based verification environments from scratch. Experience with Design verification of ta-center applications like Video, AI/ML and Networking designs. Experience in Mercurial (Hg), Git or SVN. Experience with low power design. Experience working across and building relationships with cross-functional...