Senior Design Verification Engineer

Senior Verification EngineerLocation: Bangalore/HyderabadExperience: 4+ years1Must have very good System Verilog/UVM experienceMust have expertise in PCI gen6 and CXL3.1or Ethernet bus protocolsHave experience in IP/SoC VerificationExpertise in AMBA/AXI bus protocols and ARM CPUExperience in developing functional verification environments including the...

Job Title: AMS Verification EngineerExperience Required: Minimum 4 years relevant experience is required.Location: Bangalore, Hyderabad, Noida, Chennai, Ahmedabad, PuneKey Responsibilities:Min 4 Years of overall experience in ASIC VerificationShould have worked on AMS Verification for minimum of 2 yearsDevelop and execute verification plans for AMS...

Position: AMS Verification Engineers Experience: 5+ YearsLocation: Bangalore, Hyderabad, Ahmedabad, NoidaKey Responsibilities:Lead the planning, development, and execution of AMS verification strategies for analog/mixed-signal IPs and SoCs.Define and implement verification plans, including testbenches, stimulus generation, and checking strategies.Develop and...

Senior Digital IC Design Engineer (BMS)Job Description PI Semi is founded by a team of industry veterans with a successful track record designing andmarketing quality analog and mixed signal ICs, a market enjoying $60B in its annual turnover worldwide. Our core IPs and products support such applications as highspeed optical communications, RF bias for 5G...

Exp: 8+ YearsLocation: BangaloreJD:Key Responsibilities:· Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.· Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.· Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe...

• PNR Leads Required with Shorter Notice period to lead a Team for a Long-Term Project.• Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. • Experience in PnR tools like ICC/Innovus with regards to physical convergence must. • Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV. • Good overall...

Responsibilities:You should be a verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/PCIe/CXL, DDRx/LPDDRx integration verification in SoC RTL.Project experience with ARM based ecosystem components (A-series ARM Cores, SMMU, GIC, Core sight, NIC and other complex bus...

Experience: 3 - 6 YearsNotice period: ImmediateLocation: Bangalore & HyderabadResponsibilitiesMandatory Experience in Full Chip Timing.Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization.Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing...

Areas of Responsibility:Participate and contribute to requirements elicitation and definition phase of the project.Develop Test Architecture, Specification and Test script for MCAL device drivers.Software Verification of device drivers (Eg: MEM, MEMACC, FEE, SPI, LIN, DIO, ICU, ADC, CAN, DMA and MCU etc.) and safety software in an independent/RTOS...

Should be able to handle Full chip hashtagAdded advantage for #Innovus with Minimum 4 years #PnR (timing/congestion/CTS issues), understanding of hashtag#IO ring,#package support, multi hashtag#voltage design.Deep understanding of the concepts related to hashtag#synthesis, place & route, hashtag#CTS, timing convergence, IR/EM checks and signoff DRC/LVS...