SignOff Semiconductors | Synthesis Design Engineer | bangalore

1 month ago


bangalore, India SignOff Semiconductors Full time

Job Description:

  • Responsible for Front End Implementation of IPs which includes synthesis, LEC, CLP, pre-layout STA and post-layout STA/Timing closure.
  • Collaborate with Design Team and PNR Teams to achieve timing closure.
  • Understand duration required, plan and execute as per schedule.
  • Complete quality delivery for synthesis and timing closure.
  • Debug and resolve technical issues.


Requirement:

  • Highly experienced in synthesis, LEC, CLP and timing closure.
  • Preferred top level or SOC level experience.
  • Have handled blocks with complex designs, high frequency clocks and complex clocking.
  • Complete understanding of timing constraints, low power aspects and DFT Concepts.
  • Have debug experience to solve issues.
  • Scripting and Automation.
  • Minimum years of experience 4+



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