Senior design verification engineer
1 month ago
Responsibilities -
4+ Years of Experience in Design Verification
Proficiency in System Verilog
Define products test plans & cases from scratch
Proficiency in UVM methodology
Extensive experience in building digital verification frameworks from scratch, using UVM methodology
Proficiency in System Verilog Assertions
Must be able and willing to investigate in detail the designed product and develop a tailored and comprehensive verification bench
Must have good problem-solving skills & Debugging
Must have good communication skills and ability to work effectively in a team
Must be self-motivated to produce best quality results
Good to have exp in protocols like Ethernet /DDR/PCI
Must have experience in AXI/AXB
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