Verification Engineer for SystemVerilog Designs

4 days ago


Hyderabad, Telangana, India Coders Brain Technology Private Limited Full time

Coders Brain Technology Private Limited invites applications from experienced VLSI Front-End Design Verification Engineers for the position of Senior Verification Engineer. This is a great opportunity to work on cutting-edge projects and receive a salary of ₹12,50,000 per annum.

Job Overview:

The selected candidate will lead a team of verification engineers in designing and verifying front-end designs using SystemVerilog (SV) and UVM frameworks. A strong understanding of verification methodologies and protocols is essential for this role.

Key Responsibilities:

  • Execute front-end design verification using SystemVerilog (SV) and UVM frameworks.
  • Leverage expertise in SystemVerilog (SV) and UVM-based verification methodologies to drive innovation in verification processes and methodologies.
  • Develop and implement verification plans, test cases, and testbenches to meet project requirements.
  • Collaborate with design and architecture teams to ensure verification coverage and identify design bottlenecks.

Requirements:

  • 10+ years of experience in VLSI front-end design verification.
  • Expertise in SystemVerilog (SV) and UVM-based verification methodologies.
  • Proven track record of delivering high-quality results under tight deadlines.

What We Offer:

  • A highly competitive salary of ₹12,50,000 per annum.
  • A comprehensive benefits package including medical insurance, retirement savings plan, and paid time off.
  • Opportunities for career growth and professional development.


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