Front-End Design Verification Specialist
3 weeks ago
Coders Brain Technology Private Limited is seeking a seasoned VLSI Front-End Design Verification Engineer with expertise in SystemVerilog (SV) and UVM-based verification methodologies. This role offers a competitive salary of ₹15,00,000 per annum.
Job Description:
We are looking for a candidate who can execute front-end design verification using SystemVerilog (SV) and UVM frameworks. The ideal candidate will have a strong technical background, proven experience in leading teams, and hands-on verification expertise.
Key Responsibilities:
- Design Verification (DV): Execute front-end design verification using SystemVerilog (SV) and UVM frameworks.
- Protocol Expertise: Experience in working with any industry-standard protocol will be an added advantage.
- Leadership and Team Handling: Manage and mentor a team of verification engineers, ensuring deliverables are met with high quality and within timelines.
- Collaboration: Work closely with design and architecture teams to ensure verification coverage and identify design bottlenecks.
- Process Improvements: Drive innovations in verification processes and methodologies for improved efficiency and quality.
Technical Skills Required:
- Proficiency in SystemVerilog (SV) and UVM-based verification methodologies.
- Hands-on experience with verification environments, test benches, and debugging tools.
- Knowledge of protocols like PCIe, USB, Ethernet, AMBA, etc., is a plus.
- Strong analytical and problem-solving skills.
Benefits:
- A comprehensive benefits package including medical insurance, retirement savings plan, and paid time off.
- Opportunities for career growth and professional development.
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