Senior Formal Verification Engineer
3 weeks ago
**Job Title:** Senior Formal Verification Engineer - Design and Verification Expert
**About BITSILICA:
BITSILICA is a leading company in the field of digital design and verification. We are currently seeking a highly skilled Senior Formal Verification Engineer to join our team.
**Estimated Salary:** $140,000 - $180,000 per year
**Job Description:
The Senior Formal Verification Engineer will be responsible for developing and implementing formal verification environments for semiconductor IP and design blocks. This role requires strong expertise in digital logic design and computer architecture, as well as experience with industry-standard formal verification tools such as Cadence Jasper Gold, Synopsys VC Formal, or Siemens Questa Formal.
**Responsibilities:*
- Develop test plans and verification methodologies to verify microarchitecture and design
- Implement and improve functional verification in semiconductor IP and design blocks
- Collaborate with cross-functional teams to deliver high-quality code
**Requirements:*
- Bachelor's or Master's Degree in Electrical/Electronics
- 6+ years of hands-on experience in Formal Verification
- Strong understanding of Formal Verification using SystemVerilog Assertions
- Experience with logic and SoC Verification from planning to closure
**What We Offer:
At BITSILICA, we offer a dynamic work environment, competitive salary, and opportunities for growth and development. If you are a motivated and experienced Formal Verification Engineer looking for a new challenge, please submit your application.
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