Innovation Lead semiconductor
2 days ago
Design, develop, and maintain highly configurable testbench environments for RISC-V cores and clusters using synthesizable SystemVerilog, UVM and C++.
Contribute to the CVM (C++ Verification Methodology) - a UVM-inspired framework - by applying modern C++ features to simplify testbench development and improve maintainability.
Enable integration of UVM-based block-level environments into the broader testbench framework to support hybrid simulation workflows.
Ensure testbench portability across simulators (including open-source Verilator) and commercial emulation platforms.
Develop debugging tools and automation to accelerate root-cause analysis for failures across simulation and emulation.
Experience and Qualifications
Bachelor's or Master's degree in Electronics, Computer Engineering, or a related field, with 9+ years of relevant industry experience.
Strong proficiency in modern C++ and SystemVerilog, including familiarity with verification libraries or testbench infrastructure.
Hands-on experience with SystemVerilog UVM, including environment construction and integration into larger simulation contexts.
Experience working with or contributing to custom DV methodologies (e.g., UVM, custom C++-based frameworks).
Solid understanding of software engineering principles such as design patterns (e.g., publish-subscribe), multithreaded programming, and coroutines.
Strong debugging and analytical skills across layers of abstraction — from software and compiler traces to assembly programs and RTL waveforms.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
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