Tessolve | Sr.Design Verification Engineer | bangalore

hello Connections!!Immediate hiring!!!Tessolve Semiconductors is hiring for below positionsPosition: Sr.Design Verification Engineer-Lead and aboveExperience: 8+ years to 20 yearsLocation - Bangalore/Hyderabad/NoidaNotice period: immediate to 30 days most preferable.Position Description:• To be part of a highly skilled ASIC Team working on the newest...

hello Connections!! Immediate hiring!!! Tessolve Semiconductors is hiring for below positions Position: Sr. Design Verification Engineer-Lead and above Experience: 8+ years to 20 years Location - Bangalore/Hyderabad/Noida Notice period: immediate to 30 days most preferable. Position Description: • To be part of a highly skilled ASIC Team...

Job Description:Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production.Ensure Test Coverage Goals are met at SoC Level.Addressing test quality targets in DFT architecture and test pattern generation.Leading various aspects of Test architecture including Scan&ATPG, and...

Job Description: Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production. Ensure Test Coverage Goals are met at SoC Level. Addressing test quality targets in DFT architecture and test pattern generation. Leading various aspects of Test architecture including Scan&ATPG, and...

Senior Physical Design Engineer: Experience: 5 years to 12 years relevant experience. Location – Bangalore Tessolve Semiconductors a venture of Hero Electronix , part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and...

Hi All, we are hiring RTL Engineer with Tessolve semiconductors - Bangalore Location JD: Design RTL ASIC Engineer Location: Bangalore,HYD and Noida Experience :- 5 to 20 Years Experience and Skills Required 5 to 20 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level...

Greetings From Tessolve Semiconductors. A widely leading core semiconductor company in world wide. HIRING!.. TESSOLVE SEMICONDUCTORS PVT LTD DFT REQUIREMENT – 2024 Location – Bangalore, USA, Canada, Malaysia Experience – 5+ years to 20 years We're hiring highly skilled DFT Engineers for all the DFT Techniques (ATPG, SCAN, JTAG, MBIST ). if you're...

JOB DESCRIPTION Title/Position: Design Verification Engineers/Leads/Manager Location: PAN India Positions: 20 Type: Fulltime Interested candidates please share the CV to chandanaliz.kuruvila@tessolve.com Design Verification Engineers/Leads/Manager Technical Skillset Required: IP verification Using SV/UVM SOC Verification using C/SV VIP Integration ...

JOB DESCRIPTION Title/Position: Design Verification Engineers/Leads/Manager Location: PAN India Positions: 20 Type: Fulltime Interested candidates please share the CV to chandanaliz.kuruvila@tessolve.com Design Verification Engineers/Leads/Manager Technical Skillset Required: IP verification Using SV/UVM SOC Verification using C/SV VIP Integration ...

JOB DESCRIPTION Title/Position: Design Verification Engineers/Leads/Manager Location: PAN India Positions: 20 Type: Fulltime Interested candidates please share the CV to Design Verification Engineers/Leads/Manager Technical Skillset Required: IP verification Using SV/UVM SOC Verification using C/SV VIP Integration Interconnect Protocols: AHB,...

JOB DESCRIPTION Title/Position: Senior Verification Engineer Location: PAN India Positions: 20 Type: Fulltime Kindly share you resume to Key Skills and Responsibilities: IP verification Using SV/UVM or SOC Verification using C/SV VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2 C, UART (5+) High Speed...

JOB DESCRIPTION Title/Position: Senior Verification Engineer Location: PAN India Positions: 20 Type: Fulltime Kindly share you resume to mallika.dhamotharapandiyan@tessolve.com Key Skills and Responsibilities: IP verification Using SV/UVM or SOC Verification using C/SV VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C,...

JOB DESCRIPTIONTitle/Position: Design Verification Engineers/Leads/ManagerLocation: PAN IndiaPositions: 20Type: FulltimeInterested candidates please share the CV to chandanaliz.kuruvila@tessolve.comDesign Verification Engineers/Leads/ManagerTechnical Skillset Required:IP verification Using SV/UVMSOC Verification using C/SVVIP IntegrationInterconnect...

JOB DESCRIPTION Title/Position: Design Verification Engineers/Leads/Manager Location: PAN India Positions: 20 Type: Fulltime Interested candidates please share the CV to Design Verification Engineers/Leads/Manager Technical Skillset Required: IP verification Using SV/UVM SOC Verification using C/SV VIP Integration Interconnect Protocols: AHB, AXI, APB...

JOB DESCRIPTIONTitle/Position: Senior Verification EngineerLocation: PAN IndiaPositions: 20Type: FulltimeKindly share you resume to Key Skills and Responsibilities:IP verification Using SV/UVM or SOC Verification using C/SVVIP IntegrationInterconnect Protocols: AHB, AXI, APBSOC Interfaces: GPIO, SPI, I2C, UART (5+)High Speed Serial Interfaces: PCIe Gen 3/4...

SoC Level Verification: - **Responsibilities:** - Verify the integration of various IP blocks within the SoC. - Ensure proper functionality and communication between different IPs. - Utilize techniques such as simulation, emulation, and formal methods. - Perform power and performance analysis. - Validate system-level features and use cases. - **Required...

So C Level Verification: - **Responsibilities:** - Verify the integration of various IP blocks within the So C. - Ensure proper functionality and communication between different IPs. - Utilize techniques such as simulation, emulation, and formal methods. - Perform power and performance analysis. - Validate system-level features and use cases. ...

JOB DESCRIPTIONTitle/Position: Senior Verification EngineerLocation: PAN India Positions: 20Type: FulltimeKindly share you resume to mallika.dhamotharapandiyan@tessolve.comKey Skills and Responsibilities: IP verification Using SV/UVM or SOC Verification using C/SV VIP IntegrationInterconnect Protocols: AHB, AXI, APBSOC Interfaces: GPIO, SPI, I2C, UART...

JOB DESCRIPTION Title/Position: Senior Verification Engineer Location: PAN India Positions: 20 Type: Fulltime Kindly share you resume to Key Skills and Responsibilities: IP verification Using SV/UVM or SOC Verification using C/SV VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (5+) High Speed...

JOB DESCRIPTIONTitle/Position: Design Verification Engineers/Leads/ManagerLocation: PAN IndiaPositions: 20Type: FulltimeInterested candidates please share the CV to chandanaliz.kuruvila@tessolve.comDesign Verification Engineers/Leads/ManagerTechnical Skillset Required:IP verification Using SV/UVMSOC Verification using C/SVVIP IntegrationInterconnect...