Design Verification Engineer

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...

Talented and motivated Mid-Level CPU Subsystem Design and Verification Engineer to join our growing team. Responsibilities : Design : Participate in the design of CPU subsystems, collaborating with architects and design engineers. Contribute to micro-architectural decisions, considering performance, power, and area trade-offs. Develop detailed design...

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and...

Job Title: Design Verification Engineer Exp Level:4+yrs Location: Bangalore/Hyderabad Job Description: Responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. ...

Position Overview: We are seeking a highly skilled Senior Engineer/Architect to join our dynamic team. In this pivotal role, you will lead the design and verification of advanced integrated circuits (ICs), ensuring they meet the highest standards of quality and performance. This position offers the opportunity to work on groundbreaking projects and influence...

Design Verification Engineer - Senior / Lead / Sr. Lead Job Description: Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem solving attitude.. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification,...

SoC Verification Engineer (Formal, 6–8 Yrs) Pune/Bengaluru Experienced SoC Verification Engineers with strong expertise in Formal Verification using JasperGold. Experience: 6–8 years Must-Have Skills: JasperGold, SVA, RTL Debug Good to Have: UVM, low-power/security verification

Senior Design verification Engineer Mandatory Skill : PCIE Location : Bangalore Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write...

Hi All, ACL Digital is hiring #Senior #Design #Verification Engineer! Experience: 4 Years Location: Bangalore / Hyderabad Notice Period: Immediate to 30 Days Preferred! We're seeking experienced professionals ASIC/SoC verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a...

ACL Digital Hiring for the below requirementDesignation: DV engineersExperience: 8-10+ yearsLocation: BangaloreJob Description:1. Hands-on experiences on SV/UVM/Specman2. Familiarity with formal-based verification3. Running regression and debugging failures independently4. Experience in functional and code coverages5. Independently handling sub-module-level...