Senior Design Verification Engineer

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

Position Overview: We are seeking a highly skilled Senior Engineer/Architect to join our dynamic team. In this pivotal role, you will lead the design and verification of advanced integrated circuits (ICs), ensuring they meet the highest standards of quality and performance. This position offers the opportunity to work on groundbreaking projects and influence...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe,...

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...

Hi All, ACL Digital is hiring #Senior #Design #Verification Engineer! Experience: 4 Years Location: Bangalore / Hyderabad Notice Period: Immediate to 30 Days Preferred! We're seeking experienced professionals ASIC/SoC verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a strong...

Senior Design Verification Engineer Job Description: SV / UVM Test bench development and test cases coding. Code and Functional coverage analysis and closure. Work with team for verification closure. Experience with python or any other scripting language is a plus. Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an...

Senior Design Verification Engineer Location: Bangalore. Experience: 4 to 10 Years. Notice Period: Any. Perform verification of complex digital designs at block and system level. Develop testbenches using SystemVerilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve...

Senior Design Verification EngineerJob Description:SV / UVM Test bench development and test cases coding.Code and Functional coverage analysis and closure.Work with team for verification closure.Experience with python or any other scripting language is a plus.Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage.Experience: 3 to 8...

Key job responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test...

Key job responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test...