Senior Memory Architect Leader
3 weeks ago
Estimated Salary: $250,000 - $350,000 per year
About Micron TechnologyMicron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. Our vision is to transform how the world uses information to enrich life for all.
We are an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. For over 45 years, we have redefined innovation with the world's most advanced memory and semiconductor technologies.
Job DescriptionAs a Director/Senior Manager - HBM Memory Circuit Design Verification, you will work in a highly innovative, motivated, young, and dynamic design team capable of verifying complete products using state-of-the-art memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure timely delivery of a functionally correct design.
Responsibilities:- Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes.
- Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs.
- Develop test cases/stimuli to increase functional coverage for all DRAM and emerging memory architectures and features.
- Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.
- Cowork with international colleagues on developing new verification flows to take on challenges in DRAM and emerging memory design.
- Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
- Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures.
- Attract, recruit, train, engage, and retain top talent to build a world-class verification team.
- Familiarity with DRAM operation and JEDEC specifications, preferably with HBM product family.
- Extensive experience with CMOS circuit design and good understanding of semiconductor device physics.
- Knowledge and experience in digital (Verilog) and analog (FastSpice & Hspice) modeling and simulations.
- Experience in System Verilog, PLI coding.
- Experience in UVM Test Bench.
- Experience in AMS verification and co-simulation.
- Good verbal and written communication skills with the ability to effectively synthesize and convey complex technical concepts to other partners and leadership.
- Strong track record of innovation and problem-solving in high-performance memory development.
- Bachelor's degree or higher in Electrical Engineering or related field.
- 15+ years of relevant engineering experience.
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