Gate Level Simulation Expert
3 days ago
We are seeking a skilled Gate Level Simulation Expert to lead our verification efforts. As a gate level simulation expert, you will be responsible for verifying and debugging low-power designs, collaborating with cross-functional teams, and developing gate-level simulation strategies.
- Verify and debug low-power design using industry-standard protocols and interfaces
- Develop and implement gate-level simulation strategies for complex digital designs
- Conduct gate-level simulations to verify functionality and performance of digital designs
Expertise in SV and UVM is crucial in optimizing and enhancing the gate-level simulation process. You will also ensure compliance with industry standards and best practices in gate-level simulation. A comprehensive understanding of static timing analysis (STA) and power analysis is essential for this role.
Key responsibilities include:
- Develop and execute comprehensive test plans for gate-level simulations
- Analyze simulation results, debug failures, and propose design improvements
- Ensure thorough coverage and validation of all critical paths and corner cases
- Automate simulation workflows to enhance efficiency and reproducibility
Our ideal candidate has experience in gate-level simulation, verification, and debugging, as well as expertise in SV and UVM. They will collaborate closely with our team to deliver high-quality solutions.
Why Choose Us?
At our organization, we prioritize innovation and excellence in delivering technology solutions. We are committed to providing exceptional services that exceed our clients' expectations.
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