Power Simulation Engineer
3 days ago
Job Role Summary
We are seeking a talented and skilled professional to fill the role of Power Simulation Engineer.
Job DescriptionThe ideal candidate will have experience in power domains, HW programming guide sequences, and low power design techniques. The responsibilities will include understanding of power domains and HW programming guide sequences, develop test plan to verify all low power states, own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals.
The candidate will also be responsible for exploring innovative dynamic or static methodologies by engaging with EDA vendors, strong System Verilog/UVM based verification skills, Experience with Assertion coverage-based verification methodology, Experience in formal / static verification methodologies, good understanding of low power design techniques, proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
Required Skills and Qualifications- Experience with UPF/CPF based power aware verification.
- Experience with Synopsys NLP (native Low Power) tool.
- Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python.
- Proficiency in Low-Power standards like UPF/CPF.
- Working knowledge on UPF based RTL / PGPIN simulations.
- Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs).
The successful candidate will have excellent analytical and problem-solving skills with a focus on power optimization.
OthersWe offer a competitive compensation package and a collaborative work environment.
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