Expert Digital Architect

3 days ago

Bharatpur, Rajasthan, India beBeeHardware Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Senior Hardware Engineer

Job Overview:

This position involves the development of complex hardware architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture and multi-level caches, multiple clocks and resets, high-speed interfaces, peripherals.

The chosen candidate would need to contribute to, and manage a team for, the development of hardware architecture, micro-architecture, and design of SoCs which include RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories, along with the integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for leading a project through the entire product development process.

Key Responsibilities:
  • Lead the development and execution of Wireless SoC's from definition, through execution, and into production
  • Define and plan the technical direction of the SoC requirements
  • Coordinate with cross-functional teams (such as software) on dependencies and resource requirements
  • Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse
  • Drive design action items to closure and perform prudent escalation when necessary
  • Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross-functional teams
  • Follow established quality procedures and processes to achieve first tapeout
Requirements:
  • Candidate must have 12+ years of experience in industry, preferably in full-chip development cycle
  • Hands-on experience in architecture, micro-architecture, digital design processes
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of processors like RISC-V and ARM processors
  • Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
  • Knowledge of DFT including Scan, ATPG, MBIST
  • Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
  • Knowledge of hardware accelerators
  • Knowledge of Verilog and System Verilog
  • Knowledge of scripting languages like Perl, Python, Tcl, shell
Benefits & Perks:
  • Equity Rewards (RSUs)
  • Employee Stock Purchase Plan (ESPP)
  • Insurance plans with Outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy
  • Childcare support

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