Chief Digital Fault Architect

2 weeks ago

Erode, Tamil Nadu, India beBeeDftLeader Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Job Description

As a Lead DFT Engineer, you will be responsible for driving DFT architecture, planning, and implementation across complex SoC/ASIC designs. You will work closely with cross-functional teams to ensure world-class testability and manufacturability of silicon products.

  • Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Lead implementation and verification of DFT features like scan insertion and compression (e.g., EDT), ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), and IJTAG (1687).
  • Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
Required Skills & Qualifications
  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
Why Join Us?
  • Work on high-performance, next-gen SoCs and ASICs.
  • Collaborate with top-tier engineers and global semiconductor leaders.

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