Lead ASIC Implementation Engineer

3 weeks ago


Bengaluru, Karnataka, India Cisco Full time

Job Description

Cisco is seeking a highly skilled Lead ASIC Implementation Engineer to join our development organization in Bangalore, India. As a key member of the team, you will be responsible for driving design-for-test requirements and implementing cutting-edge next-generation networking chips.

Key Responsibilities:

  • Analyze current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related tools, flow, and methodology.
  • Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
  • Drive methodologies and 'best known methods' to streamline and automate physical design work.
  • STA setup, convergence methodology, reviews, and sign-off for Multi-Mode and Multi-corner designs.
  • Good at Timing ECO implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
  • Work on automation scripts within STA tools for methodology development.
  • Evaluate multiple timing methodologies/tools on different designs and technology nodes.

Requirements:

  • 8+ years of related work experience with a broad mix of technologies including all aspects of ASIC Physical implementation, Hierarchical design implementation approach, Timing closure, physical convergence, Power Integrity Analysis.
  • Experience with large designs (> 100M gates) utilizing state-of-the-art sub 16/14/7/5/3nm technologies.
  • Familiarity with various process-related design issues including Design for Yield and Manufacturability, multi-Vt strategies.
  • Hands-on experience with the following Tool sets: Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2, Synthesis Tools: Synopsys DC/FC, Formal Verification: Synopsys Formality and Cadence LEC, Static Timing verification: Primetime-DMSA, Power Integrity: Apache Redhawk, Physical Design Verification Synopsys ICV, Mentor Calibre.

What We Offer:

  • An estimated salary of ₹45,00,000 - ₹65,00,000 per annum, depending on experience.
  • A competitive benefits package, including medical, dental, and vision insurance, retirement savings plan, and paid time off.


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