ASIC Engineering Technical Lead
2 weeks ago
About Cisco Silicon One
Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.
Job Summary
We are seeking an experienced ASIC Design for Test Hardware Engineer to join our Silicon One development organization in Bangalore, India. As an ASIC Implementation Technical Lead, you will be responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Key Responsibilities
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Requirements
- Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10 years of experience.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design
Preferred Skills
- Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
- DFT CAD development – Test Architecture, Methodology and Infrastructure
- Test Static Timing Analysis
- Post silicon validation using DFT patterns.
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