Leading ASIC Design Verification Engineer for SoC Level Protocols
2 weeks ago
We are seeking a seasoned professional to fill the role of ASIC Design Verification Engineer at Tessolve. In this position, you will be responsible for leading the verification process for our high-speed protocols and ensuring the highest quality in our ASIC designs.
The ideal candidate will have extensive experience in various verification methodologies, including functional, formal, CPU, and GLS verification. Strong understanding of SystemVerilog and Universal Verification Methodology (UVM) is required. Additionally, proficiency in tools such as VCS, ModelSim, Questa, JasperGold, VC Formal, Synopsys, Cadence, or Mentor is necessary.
As an ASIC Design Verification Engineer, you will develop and execute comprehensive verification plans for our ASIC designs. This includes utilizing various verification techniques, implementing IP verification strategies for high-speed protocols, and collaborating with design and architecture teams to understand design specifications and requirements.
We offer a competitive salary range of $120,000 - $180,000 per annum, depending on experience and qualifications. If you are passionate about delivering high-quality results and contributing to the growth of our company, we encourage you to apply.
Responsibilities:
- Develop and execute comprehensive verification plans for ASIC designs
- Utilize various verification methodologies, including functional, formal, CPU, and GLS verification
- Implement IP verification strategies for high-speed protocols
- Collaborate with design and architecture teams to understand design specifications and requirements
- Create, maintain, and enhance testbenches and simulation environments
- Perform coverage analysis and closure to ensure all scenarios are tested
- Debug and resolve complex design and verification issues
- Document and present verification results to cross-functional teams
Required Skills and Qualifications:
- 4+ years of experience in ASIC design verification
- Strong understanding of SystemVerilog, UVM, and related verification methodologies
- Proficiency in tools such as VCS, ModelSim, Questa, JasperGold, VC Formal, Synopsys, Cadence, or Mentor
- Experience with high-speed protocols such as PCIe, USB, Ethernet, DDR, MIPI, SATA, SerDes, etc.
- SoC level protocols: AMBA (AXI, AHB, APB), ARM CoreSight, etc.
- Techniques: Assertion-based verification, Random and directed test methodologies, Power-aware verification, Performance and throughput analysis, Emulation and prototyping
Benefits:
- Competitive salary range of $120,000 - $180,000 per annum
- Ongoing training and development opportunities
- A dynamic and supportive work environment
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Bengaluru, Karnataka, India Tessolve Full timeJob OverviewWe are seeking a highly skilled ASIC Design Verification Engineer with extensive experience in various verification methodologies to join our team at Tessolve.The ideal candidate will have a deep understanding of functional, formal, CPU, and GLS verification. This role requires expertise in SoC and IP level verification, particularly with...
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