Advanced ASIC Design Verification Engineer
1 month ago
We are seeking a seasoned ASIC Design Verification Engineer to join our team at Tessolve. As an expert in semiconductor manufacturing, you will play a crucial role in ensuring the highest quality of our ASIC designs.
Responsibilities- Develop and execute comprehensive verification plans for ASIC designs.
- Utilize various verification methodologies, including functional, formal, CPU, and GLS verification.
- Conduct SoC level verification, ensuring integration and functionality of multiple IPs.
- Implement IP verification strategies for high-speed protocols such as PCIe, USB, Ethernet, DDR, MIPI, and others.
- 5+ years of experience in ASIC design verification.
- Strong understanding of OO concepts and proficient in SystemVerilog, UVM (Universal Verification Methodology), C/C++.
- Experience with simulation tools: VCS, ModelSim, Questa, etc., formal verification tools: JasperGold, VC Formal, etc., and GLS tools: Synopsys, Cadence, or Mentor tools.
As a valued member of our team, you can expect:
- A competitive salary range of $120,000 - $180,000 per annum.
- A comprehensive benefits package, including health insurance, retirement plan, and paid time off.
- Opportunities for professional growth and development through training and mentorship programs.
Tessolve is committed to fostering a workplace that celebrates diversity and inclusivity. We believe that diverse teams drive innovation and success, and we aim to create an environment where all employees feel valued and respected.
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