Verification Engineer for Complex ASICs
1 day ago
Company Overview
Sykatiya Technologies is a leading provider of innovative solutions in the field of semiconductor verification.
Job Description
We are seeking an experienced Verification Engineer to join our team. The ideal candidate will have a strong background in digital design and experience with System Verilog, UVM methodology, and front-end simulator tools (VCS/NC). Responsibilities include:
- Designing and developing block-level verification environments for sub-systems and full-chip using System Verilog and UVM methodology
- Creating verification suites/tests for ASICs that enable faster, denser, feature-rich systems
- Verifying large ASIC blocks independently and rapidly, sign-off for tape-out, and analyzing code coverage, functional coverage, and Gate level simulation
- Developing Perl, Python, and/or shell scripts to improve current verification infrastructure/methodology
Required Skills and Qualifications
To be successful in this role, you will need:
- A minimum of 4 years of experience in real-time projects
- Expertise in ASIC verification using System Verilog
- Experience in constrained-random verification (strongly preferred)
- Familiarity with verification methodologies like OVM/VMM/UVM
- Strong problem-solving and ASIC debugging skills
Benefits and Others
We offer a competitive salary range of $120,000 - $180,000 per annum, based on experience, as well as opportunities for growth and professional development. If you're passionate about working on complex ASICs and want to join a dynamic team, please submit your application.
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