ASIC Design Verification Expert

1 month ago

Bengaluru, Karnataka, India Tessolve Full time
Senior ASIC Design Verification Engineer Job Description

At Tessolve, we are seeking a seasoned ASIC Design Verification Expert to join our team. This role is perfect for an experienced professional who wants to take their career to the next level and contribute to cutting-edge projects.

We offer a highly competitive salary range of $120,000 - $180,000 per year, depending on experience and qualifications. If you're passionate about verification and have what it takes to excel in this field, we encourage you to apply.

Job Summary:

This is a mid-senior level position that requires extensive knowledge of various verification methodologies, including functional, formal, CPU, and GLS verification. As an ASIC Design Verification Expert, you will be responsible for developing and executing comprehensive verification plans for ASIC designs. Your expertise should include SoC and IP level verification, with a focus on high-speed protocols.

Responsibilities:
  • Develop and execute detailed verification plans specific to each project.
  • Collaborate with design and architecture teams to ensure seamless integration and functionality of multiple IPs.
  • Implement verification strategies for high-speed protocols such as PCIe, USB, Ethernet, DDR, MIPI, and others.
  • Create, maintain, and enhance testbenches and simulation environments.
  • Perform coverage analysis and closure to ensure all scenarios are tested.
  • Debug and resolve complex design and verification issues.
  • Mentor junior engineers and contribute to the continuous improvement of verification processes.
Requirements:

To be successful in this role, you should possess:

  • A minimum of 5+ years of experience in ASIC design verification.
  • Expertise in SystemVerilog, UVM (Universal Verification Methodology), C/C++.
  • Strong understanding of OO (Object-Oriented) concepts.
  • Experience in writing assumptions, sequences, virtual sequences, tests, and coverage closures.
  • Familiarity with UVM factory and configurations, UVM callbacks.
  • Proficiency in simulation tools such as VCS, ModelSim, Questa, etc.
  • Formal verification tools: JasperGold, VC Formal, etc.
  • GLS tools: Synopsys, Cadence, or Mentor tools.
  • Debug tools: Verdi, DVE, SimVision, etc.
  • Coverage tools: Specman, Coverage Analyzer, etc.
Preferred Qualifications:

Prior experience in leading verification projects is highly desirable. Contributions to industry standards or verification methodologies, as well as publications or patents in the field of ASIC verification, will be considered favorably.

About Us:

Tessolve is a semiconductor manufacturing company dedicated to fostering a workplace that celebrates diversity and inclusivity. We believe that diverse teams drive innovation and success. We strive to create an environment where all employees feel valued and respected.

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