Design Lead

24 hours ago

Aurangabad, Maharashtra, India beBeeSenior Full time ₹ 25,00,000 - ₹ 30,00,000

Job Opportunity:

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We are seeking an accomplished Senior Physical Design Engineer to join our team. With over 10 years of experience in the RTL to GDS flow, this individual will be responsible for delivering high-quality projects on time.

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The ideal candidate will possess strong scripting skills and hands-on experience with 3nm and 5nm nodes. They will also have a proven track record in physical design, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.

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Main Responsibilities:

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  • Perform physical design efforts from RTL to GDS ensuring high-quality and timely delivery of projects">
  • Conduct floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification">
  • Develop and maintain scripts for automation of physical design tasks improving efficiency and reliability">
  • Collaborate with RTL designers, DFT engineers, and verification teams to resolve design issues and achieve timing closure">
  • Conduct power, performance, and area (PPA) optimization to meet design specifications">
  • Review and analyze physical design reports including timing, signal integrity, and power analysis, and implement necessary changes">
  • Mentor junior engineers fostering a culture of knowledge sharing and continuous improvement">
  • Stay updated with the latest advancements in physical design tools and methodologies and integrate best practices into the design process">
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Requirements:

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  • Bachelor's or Master's degree in Electrical Engineering Computer Engineering or a related field">
  • 10+ years of experience in physical design with a comprehensive understanding of the RTL to GDS flow">
  • Hands-on experience with 3nm and 5nm process nodes">
  • Expertise in physical design tools such as Cadence Innovus Synopsys ICC2 or similar">
  • Strong proficiency in scripting languages such as Tcl Perl or Python for automation of design tasks">
  • Proven experience in achieving timing closure optimizing for PPA and resolving complex design issues">
  • Solid understanding of digital design principles including clock distribution signal integrity and power analysis">
  • Excellent problem-solving skills and attention to detail">
  • Strong communication skills with the ability to work effectively in a team environment and collaborate with cross-functional teams">
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Preferred Skills:

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  • Knowledge of low-power design techniques and methodologies">
  • Familiarity with version control systems and collaborative development tools">
  • Experience with physical verification tools such as Calibre or Mentor Graphics">

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