Senior Memory Verification Engineer
4 weeks ago
About the Role
Cadence Design Systems, Inc. is seeking a highly skilled Senior Memory Verification Engineer to join our team. As a key member of our Memory Domain team, you will be responsible for driving the development of our Verification IP (VIP) portfolio, with a focus on Memory protocols such as SDRAM, SGRAM, and DFI.
Key Responsibilities
- Develop and lead large-scale verification environments using System Verilog and UVM methodology
- Collaborate with cross-functional teams to ensure customer success and drive product adoption
- Provide technical expertise and training to field engineers and customers on Memory protocols and VIP portfolio
- Translate high-level customer requirements into technical specifications and drive product definition
Requirements
- At least 4-8 years of experience in Design and Verification, with a strong background in Memory protocols
- Excellent problem-solving and debugging skills, with the ability to work independently and collaboratively
- Strong written, verbal, and presentation skills, with the ability to communicate complex ideas to senior-level stakeholders
About Cadence
Cadence is a pioneering leader in electronic design, with a rich history of innovation and expertise in computational software. Our team is passionate about delivering cutting-edge technology and solutions that make a real impact on the world.
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