Design Verification Project Manager

1 week ago


Thiruvananthapuram, Kerala, India beBeeVerification Full time ₹ 25,00,000 - ₹ 30,00,000
Project Manager for Verification Engineering

We are seeking a seasoned project manager to lead our verification engineering projects, driving technical leadership, project execution, and team management within the Design Verification domain.

  • The successful candidate will oversee end-to-end project delivery, ensuring timely completion of high-quality results.
  • Responsibilities include defining verification strategies, test plans, coverage goals, and closure metrics in alignment with company standards.
  • The ideal candidate will provide technical guidance on SystemVerilog, UVM-based testbench development, coverage closure, debugging, and verification methodologies.

Key Skills and Experience:

  • 14 to 20+ years of experience in Design Verification (IP / Subsystem / SoC level).
  • Strong expertise in SystemVerilog, UVM, SVA, and coverage-driven verification.
  • Hands-on knowledge of AMBA protocols (AXI, AHB, APB) and Memory/DRAM verification flows.
  • Experience with Gate Level Simulation (GLS), Low Power (UPF), and Formal Verification is a strong plus.
  • Exposure to EDA tools such as Cadence Xcelium, Synopsys VCS, and Verdi.
  • Proven experience in project/program management, leading DV teams (10+ engineers).
  • Strong stakeholder management, planning, and execution skills.
  • Excellent communication and leadership skills.

Benefits of Joining Our Team:

  • Opportunity to work on cutting-edge memory and SoC verification projects.
  • Lead high-impact DV programs with global exposure.
  • Collaborate with a technically strong, innovative team.


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