
Chief Design Verification Engineer
7 days ago
Design Test Solutions
With a strong background in DFT architectures and methodologies, including scan insertion & verification, ATPG (Automatic Test Pattern Generation), MBIST (Memory Built-In Self-Test), JTAG / Boundary Scan, you will work with our team to deliver high-quality test solutions.
You will have a solid understanding of the SoC design cycle, RTL to GDSII flow, and test requirements. This includes experience with industry-standard DFT tools from Cadence, Synopsys, and Mentor Graphics, as well as a strong ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.
A key member of our technical team, you will collaborate with RTL designers, verification engineers, and physical design teams to ensure seamless integration of DFT solutions.
Requirements:
- DFT Architectures and Methodologies: Scan insertion & verification, ATPG (Automatic Test Pattern Generation), MBIST (Memory Built-In Self-Test), JTAG / Boundary Scan
- Industry-standard DFT Tools: Cadence, Synopsys, and Mentor Graphics
- Scripting Languages: Python, Perl, and TCL
Benefits:
- Collaborative team environment
- Opportunities for professional growth and development
- Autonomy to work on challenging projects
What We Offer:
- A competitive salary and benefits package
- The opportunity to work with a talented team of professionals
- A dynamic and supportive work environment
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