Digital Circuit Design Specialist

2 days ago

Varanasi, Uttar Pradesh, India beBeeTestEngineering Full time ₹ 1,20,00,000 - ₹ 1,50,00,000

Job Summary:

We are seeking a highly skilled ASIC Test Engineer to develop and execute comprehensive test plans for the development of complex ASICs.

The ideal candidate will have a strong background in test engineering, digital design, and a proven track record of delivering high-quality results.

  • Develop and implement robust test plans to ensure thorough testing of functionality and performance.
  • Design and implement efficient test fixtures and software to support automated testing.
  • Collaborate with cross-functional teams to identify and resolve technical issues.
  • Analyze test results and provide recommendations for process improvements.

Key Responsibilities:

  • Internal loopback, SCAN (stuck-at and transition delay), Pre & Post-trim including temperature sensors, IO DC parametric tests, Process monitor / ring oscillator tests.
  • SERDES (CPRI, PCIE): Internal & external loopback – external loopback at package only, IO DC parametrics tests, Register/PLL lock checks using either APB or iJTAG for access.
  • ATPG (Automatic Test Pattern Generation): Stuck-at, Transition Delay, Cell-aware / Small Delay Defect, Memory Built-in Self-Test (MBIST) & BISR (Built-in Self Repair), Logic Built-in Self-Test (LBIST).
  • Boundary Scan (BSDL, Boundary Scan Description Language)) - IEEE1149.1 & IEEE1149.6, Programming LTU chip, Process Monitors (ProteanTec / Synopsys).
  • High Voltage Stress Testing – Cyclic Alternating Voltage Stress per TSMC, Very Low Voltage (VLV) Testing, IO Parametric Tests – leakage, Vix, Vox, IDD – quiescent/gross, functional/dynamic, sleep.
  • Top Level Verification (TLV) functional patterns, e.g., Path Delay, if any, Processor Performance (Coremark/Dhrystone) patterns, Temperature Sensor(s) – SoC - calibration & reading.
  • Characterization & Correlation – perform characterization across PVT, correlate against golden data, Production Test & Yield Ramp – optimize test time, support binning, yield analysis.
  • Failure Analysis Support – debug routines (shmoo, scan diagnosis), provide reports.

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