Chief Digital Fault Tolerance Specialist

6 days ago


Anantapur, Andhra Pradesh, India beBeeDft Full time ₹ 22,50,000 - ₹ 37,50,000
Lead DFT Architect

We are seeking a highly skilled individual to drive Digital Fault Tolerance (DFT) architecture, planning, and implementation across complex System on Chip (SoC)/Application Specific Integrated Circuit (ASIC) designs.

This is a leadership role that requires technical expertise, collaboration with cross-functional teams, and ensuring world-class testability and manufacturability of silicon products.

  • Main Responsibilities:
  • Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Implement and verify DFT features like scan insertion and compression, Automatic Test Pattern Generation (ATPG), Memory BIST, boundary scan, and Inter-Integrated Junction Technology (IJTAG).
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Develop and maintain DFT automation scripts and infrastructure.
  • Key Skills and Qualifications:
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Familiarity with scripting languages (Python, Perl, Tcl) for flow automation.

PREFERRED QUALIFICATIONS:

  • Experience with hierarchical DFT methodologies.
  • Exposure to post-silicon validation and failure analysis.


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