Distinguished Digital Fault Tolerance Architect

11 hours ago

Anantapur, Andhra Pradesh, India beBeeDigitalFaultTolerance Full time ₹ 15,00,000 - ₹ 20,00,000

Senior Digital Fault Tolerance Engineer Position

This role requires a minimum of 3 years experience in the field.

Main Responsibilities:

  • We are looking for an experienced DFT architect to develop and implement digital fault tolerance architectures for ASIC/SoC designs.
  • The ideal candidate will have expertise in inserting and verifying scan chains, boundary scan (JTAG), memory BIST (MBIST), logic BIST (LBIST), and other test structures.
  • The successful candidate will collaborate with RTL and physical design teams to ensure seamless integration of DFT features.
  • They will generate and validate test patterns using ATPG tools for stuck-at, transition, and path delay faults.
  • Fault simulation and coverage analysis will be performed to optimize test quality.
  • The selected candidate will support silicon bring-up and debug of test-related issues.
  • They will also work with Automated Test Equipment (ATE) teams to develop test programs and support production testing.

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