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Senior DFT Verification Engineer

1 month ago

Hyderabad, Telangana, India NVIDIA Full time
About NVIDIA

NVIDIA is a leader in the field of artificial intelligence, graphics processing, and high-performance computing. Our mission is to accelerate the world's innovation by making technology more accessible and powerful.

Job Description

We are seeking a highly skilled DFT Verification Engineer to join our team. As a DFT Verification Engineer, you will be responsible for designing and implementing verification environments for our complex semiconductor chips. You will work closely with our design and verification teams to ensure that our chips meet the highest standards of quality and performance.

Key Responsibilities
  • Design and implement verification environments for DFT features in complex IP's/Sub-systems/SOC's
  • Develop and own verification environments using UVM or equivalent
  • Build reusable bus functional models, monitors, checkers, and scoreboards
  • Own functional coverage driven verification closure and own design verification sign-offs at multiple levels
  • Collaborate closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams
Requirements
  • BSEE with 3+ or MSEE with 2+ years of experience in DFT verification or related domains
  • Strong expertise in 1149.X or 1500, DFT scan architecture, DFT clocking, and Design for debug
  • Expertise in System Verilog and verification methodologies like UVM/VMM
  • Expertise in prototyping, verification, and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc)
  • Good exposure to ASIC design methodologies: RTL design, clocking, timing, and low-power architectures
  • Strong programming/scripting skills in C++, Perl, Python, or Tcl
  • Excellent written and oral communication skills
  • Excitement to work on rare challenges
  • Strong analytical and problem-solving skills
Preferred Qualifications
  • Strong experience or interest in both DFT and RTL Verification domains
  • Knowledge in Formal verification methodologies and tools for IP and SoC level verification
  • Hands-on experience in post-silicon debug on ATE and/or system labs