Senior Verification Engineer

4 weeks ago


Hyderabad, Telangana, India Silicon Labs Full time
Senior Verification Engineer

We are Silicon Labs, a leader in secure, intelligent wireless technology. Our team is seeking a skilled Senior Verification Engineer to join our ranks.

This role involves design verification of next-generation modem sub-systems, focusing on performance, power, and functionality. As a Senior Verification Engineer, you will be responsible for developing and executing verification plans using System Verilog and UVM to validate complex ASIC/FPGA designs.

Key Responsibilities:

  • Design and implement testbenches and verification environments to ensure functional accuracy and performance.
  • Perform gate-level simulations to validate designs against their RTL implementations.
  • Collaborate with design engineers to understand requirements and resolve design issues.
  • Debug and troubleshoot complex issues, providing detailed analysis and solutions.
  • Document verification processes, methodologies, and results to ensure clarity and reproducibility.

Requirements:

  • 10+ years of professional experience in ASIC/FPGA verification with strong expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS).
  • Proven experience in developing and executing testbenches and verification environments.
  • Strong skills in performing gate-level simulations and analyzing results.
  • Excellent debugging skills with the ability to resolve complex design issues.

Benefits and Perks:

  • Equity Rewards (RSUs) and Employee Stock Purchase Plan (ESPP)
  • Insurance plans with outpatient cover and National Pension Scheme (NPS)
  • Flexible work policy and childcare support


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