Lead CPU Architectures and Designs

6 days ago

Chennai, Tamil Nadu, India beBeeLogic Full time ₹ 1,50,00,000 - ₹ 2,00,00,000

Job Opportunity

We are seeking an experienced CPU Architecture and Logic Design Lead to join our team.

Your Role and Responsibilities

  • Design Interconnect Solutions: Develop different interconnect topologies that meet bandwidth, latency, and RAS requirements.
  • Present Proposed Designs: Develop features and present proposed designs in high-level design discussions.
  • Collaborate on Micro-Architecture and RTL: Collaborate with verification, DFT, physical design, FW, and SW teams to develop features.
  • Signoff Pre-Silicon Design: Signoff pre-silicon design that meets all functional, area, and timing goals.
  • Participate in Silicon Validation: Participate in silicon bring-up and validation of hardware.

Preferred Education and Skills

Masters Degree

Required Technical Expertise

  • Processor Interconnect Design Delivery Leadership: At least 1 generation of processor interconnect design delivery leadership (e.g., UPI, AXI, AMBA, NoC).
  • SMP Coherency Expertise: Expertise of SMP coherency.
  • Different On-Chip Interconnect Topologies: Experience in different on-chip interconnect topologies (e.g., mesh, crossbar).
  • snoop and Data Network Protocols: Understanding of various snoop and data network protocols.
  • Latency and Bandwidth Requirements: Understanding of latency & bandwidth requirements and effective means of implementation.
  • Queuing Theory: Working knowledge of queuing theory.
  • numa/nuca Architecture: Understanding of numa/nuca architecture.
  • HDLs - VHDL / Verilog: Proficient in HDLs - VHDL / Verilog.
  • High Speed and Power Efficient Logic Design: Experience in high speed and power efficient logic design.
  • Verification, Validation, Physical Design Teams: Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage.
  • Physical Design Collaboration: Good understanding of physical design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design.
  • uarch, RTL Design Teams: Experience in leading uarch, RTL design teams for feature enhancements.

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