Senior Chip Designer

2 days ago

Bengaluru, Karnataka, India beBeePhysicalDesigner Full time ₹ 1,04,000 - ₹ 1,30,878
Job Description:

Seeking an experienced Physical Design Engineer to lead full-chip physical design flow from RTL to GDSII, focusing on floorplanning, integration, and signoff activities to meet aggressive PPA goals.


Key Responsibilities include driving the entire physical design process, ownership of chip-level floorplanning and partitioning, collaboration with cross-functional teams, implementation of place & route flows including timing closure, IR/EM, and congestion optimization, performing physical verification and resolving foundry violations, managing static timing analysis at top level, and handling power planning and domain implementation.


Required Qualifications include a Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field, 3–6 years of experience in physical design with at least one full chip tapeout, hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre), strong knowledge of physical design concepts including floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS, and proficiency in scripting languages like Tcl, Perl, Python, or Shell.


Experience: 3 to 6 Years.

Location: Bangalore / Hyderabad.

Notice Period: Less than 30 days

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