
Design Verification Strategist
1 day ago
Design Verification Strategist
Job DescriptionThis role will oversee the development of a comprehensive verification strategy from scratch, ensuring seamless collaboration with cross-functional teams.
The responsibilities include architecting DV methodologies, developing test plans, and implementing top-down DV flows to drive deployment across various classes of devices.
Key Responsibilities:- Architecting and executing DV strategies, flow development, and test plan creation
- Collaborating with design, architecture, system validation, and software teams to deliver high-quality verification results
- Developing and implementing robust DV testing plans, proposing suitable DV strategies, building test platforms, and ensuring quality of verification with coverage tools
- DV experience of at least 10 years in building test environments from scratch, with expertise in specifications, test plan creation, top-level testbench architecture, and associated environment leading to coverage closure
- Expertise in verification tools (e.g., Verilog, SystemVerilog, UVM, OVM) and standards-based verification like MIPI, USB3, Ethernet
- Experience in DV of power-aware designs and ability to come up with a verification strategy for new devices without legacy reference points
- Self-starter with hands-on approach and motivation to contribute individually towards exciting product opportunities
We're seeking an experienced Design Verification Strategist to join our team. If you have a passion for driving innovation and excellence in DV, we'd love to hear from you.
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