Principal Timing Closure Engineer

5 days ago

Malappuram, Kerala, India beBeeTimingspecialist Full time ₹ 1,00,00,000 - ₹ 1,50,00,000
Job Title: Principal Timing Closure Engineer - Mixed Signal SoCs

We are seeking a seasoned Timing Closure Expert to lead our synthesis, static timing and DFT efforts for an advanced mixed signal chip.

  • Develop and maintain methodology and flows related to timing verification and closure.
  • Generate block and full chip timing constraints.
  • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
Key Responsibilities Include:
  • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
  • Support digital chip integration work and flows.
Requirements:
  • Bachelor's/Master's/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
  • Knowledge of timing corners/modes and process variations.
  • Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
  • ECO timing flow
  • Strong communication skills are essential as you will interface with various groups (e.g. digital design, verification, DFT, physical design, etc.).
  • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools.

Enjoy working with leading edge technologies and take advantage of competitive compensation and medical benefits.

You will have the opportunity to make a significant impact on the success of our project by driving timely delivery of high-quality products.

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