Senior Design For Testability

3 days ago

Bengaluru, Karnataka, India beBeeEngineer Full time ₹ 20,00,000 - ₹ 25,00,000
Job Overview

The Senior/Lead DFT Engineer role requires a high level of expertise in design-for-testability implementation, ensuring thorough fault coverage through efficient scan architectures. Key responsibilities include:

  • Scan Insertion: Develop and implement robust scan designs to guarantee comprehensive test coverage.
  • DRC/Coverage Debug: Identify and rectify issues in the DFT implementation to ensure all necessary tests are met.
  • ATPG Pattern Generation: Create and generate advanced test patterns to achieve optimal fault coverage.
  • Gate Level Simulations: Conduct zero-delay and timing-delay simulations to verify the accuracy of the design.

To excel in this position, candidates should possess experience with JTAG/P1500 protocols, Perl/Tcl scripting, and a solid understanding of timing/formal verification/PD flow knowledge.

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