Digital Fault Tolerant Engineer

1 day ago

Vizag, Andhra Pradesh, India beBeeDftEngineer Full time ₹ 60,00,000 - ₹ 1,20,00,000
Job Description

As a senior engineer in the ASIC/DFT field, you will be responsible for ensuring DFT design rules and coverages are met. You will generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.

Key responsibilities include:

  • Interface with ASIC design teams to ensure seamless collaboration.
  • Develop and implement test patterns using Mentor tools.
  • Perform ATPG and MBIST verification using unit delay and min/max timing corner simulations.
  • Collaborate with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
  • Support post-silicon debug effort and issue resolution.
Required Skills and Qualifications

To be successful in this role, you will need:

  • A bachelor's degree in Computer Science or Electrical/Electronics Engineering.
  • Minimum 4-12 years' experience in ASIC/DFT simulation and silicon validation.
  • Detailed knowledge of DFT concepts, pattern simulation, Silicon debug, and yield enhancement.
  • In-depth knowledge and hands-on experience in ATPG - coverage analysis.
  • Experience with tools such as TestKompress, ETVerify, VCS, and ModelSim.
  • Expertise in scripting languages like Perl and shell is an added advantage.
Benefits

This role offers:

  • Dynamic work environment with opportunities for growth and development.
  • Good communication skills and ability to work collaboratively.
  • Ability to learn and adapt to new tools and methodologies.

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