Senior Digital Fault Tolerance Specialist

7 days ago

Vizag, Andhra Pradesh, India beBeeDftarchitect Full time ₹ 1,44,00,000 - ₹ 2,09,10,000
Job Description

We are seeking a highly skilled DFT Architect to drive the development of comprehensive DFT strategies and architectures for complex SoC/ASIC designs. As a technical leader, you will oversee the implementation and verification of various DFT features, including scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687), and more.

You will be responsible for managing the end-to-end DFT flow – from RTL to gate-level netlist and silicon bring-up – ensuring seamless integration with cross-functional teams. Your expertise in scripting languages (Python, Perl, Tcl) for flow automation is also essential.

Required Skills and Qualifications
  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX; Siemens EDA: Tessent ScanPro, MBIST, IJTAG; Cadence/others: Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows.
Benefits
  • Opportunity to lead DFT for high-performance, next-gen SoCs and ASICs.
  • Collaborate with top-tier engineers and global semiconductor leaders.
  • Competitive salary and fast-track growth opportunities.
Ongoing Development

We strive to foster a culture of continuous learning and growth. You will have the chance to develop your skills and stay up-to-date with industry developments through regular training sessions and workshops.

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