Optimizing Complex Systems-On-Chip with Expert Physical Design

5 days ago

Hyderabad, Telangana, India beBeeSenior Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

Job Title: Senior Physical Design Engineer

Job Summary:

Our organization is seeking a highly skilled Senior Physical Design Engineer to lead the physical implementation of complex systems-on-chip (SoCs) and intellectual property (IP) subsystems. The successful candidate will have a proven track record in block-level physical design, including floorplanning, placement, clock tree synthesis, routing, and physical verification.

Key Responsibilities:
  • Develop and implement block-level physical design strategies to ensure robust timing, power, and area goals.
  • Drive power grid design and electromagnetic interference (EM)/thermal analysis-aware routing strategies to ensure block-level power integrity and reliability.
  • Collaborate with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity.
  • Manage and optimize physical verification flows including design rule checking (DRC), layout versus schematic (LVS), antenna checks, and signoff.
  • Automate place-and-route (PNR) flows and develop custom scripts to improve productivity and design quality.
  • Mentor junior physical design engineers, fostering technical growth and best practices.
  • Coordinate with register-transfer level (RTL) design, static timing analysis (STA), verification, and backend integration teams for seamless block-to-chip integration.
Required Skills and Qualifications:
  • 8+ years of experience in physical design with a focus on block-level PNR for complex SoC/IP subsystems.
  • Proven expertise in block-level physical implementation, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
  • Hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre.
  • Strong understanding of power grid design, EM/thermal analysis, signal integrity, and reliability checks at the block level.
  • Experience managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area.
  • Proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development.
  • Demonstrated ability to lead block PNR efforts, coordinate with RTL designers, physical design teams, and verification groups to meet tapeout schedules.
  • Familiarity with low-power design techniques and power-aware physical implementation.

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