
Optimize Complex Digital Circuits
7 days ago
We are seeking a highly skilled Senior Physical Design Engineer to join our team. As a key member of our design team, you will be responsible for leading the physical design implementation of complex SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization.
Main Responsibilities:- Lead the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization.
- Collaborate with cross-functional teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance.
- Work closely with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top-level specifications.
- Develop and implement power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance.
- Design and optimize custom scripts in Tcl, Perl, or Python to streamline physical design tasks and improve workflow efficiency.
- 4+ years of experience in physical design engineering.
- In-depth knowledge of floor planning, power planning, PNR, and signoff checks.
- Strong experience in static timing analysis (STA), timing closure, and signal integrity.
- Expertise in power optimization techniques, UPF, including clock gating and multi-voltage domain design.
- Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, Redhawk-SC.
- Scripting skills in Tcl, Python, or Perl to enhance automation and streamline physical design tasks.
- Opportunity to work on cutting-edge projects with a talented team of designers.
- Professional development and growth opportunities.
- A competitive salary and benefits package.
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