Highly Experienced Physical Designer Wanted

4 days ago

Hyderabad, Telangana, India beBeePhysicalDesign Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Title: Physical Design Engineer

We are seeking an experienced Physical Design Engineer to join our team. The ideal candidate will have a strong background in physical design for full-chip and block-level designs, including floorplanning, placement, budgeting, clock tree planning and analysis, scan re-ordering, clock tree synthesis, placement optimizations, routing, timing and SI analysis/closure, ECO tasks, EM/IR, DRC, LVS, ERC analysis & fixes, low power solution development & implementation.

The successful candidate will have experience with EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc., and a sound knowledge of Unix/TCL/Perl.

The candidate must also have prior experience with Synopsys/Cadence/Mentor place and route tools and have completed designs in 16nm and/or 7nm.

In addition, the ideal candidate will be proficient in Unix/TCL/Perl, have good communication and presentation skills, and possess strong interpersonal and problem-solving skills.

Responsibilities:

  • Lead all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation.
  • Collaborate closely with the methodology team to solve implementation challenges & provide inputs to improve the Physical design flow.
  • Develop and implement design automation solutions.
  • Contribute to the development of new technologies and methodologies to improve the efficiency and effectiveness of the physical design process.

Requirements:

  • 4+ years' experience in ASIC physical design.
  • Experience with block implementation, extraction, timing, and/or full-chip designs.
  • Strong hands-on TCL/Perl development skills.
  • Good communication and presentation skills.
  • Proficient in Unix/TCL/Perl.

Preferred Qualifications:

  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project.
  • Track record of taping out complex chips on advanced process nodes.

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