Highly Skilled Design Professional Wanted
7 days ago
The ideal candidate for this Senior Physical Design Engineer role will have in-depth knowledge of floor planning, power planning, PNR, and signoff checks.
Key Responsibilities:- Leads the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization to meet performance per area (PPA) goals.
- Collaborates with RTL, DFT, and IP teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance.
- Works closely with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top-level specifications.
- Manages clock tree synthesis, manages clock skew, insertion delay, and ensures timing closure across all corners and modes. Addresses timing violations and signal integrity issues.
- Develops and implements power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance.
Experience in static timing analysis (STA), timing closure, and signal integrity is essential for success in this role. Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, and Redhawk-SC, is also required.
Requirements:- In-depth knowledge of floor planning, power planning, PNR, and signoff checks.
- Strong experience in STA, timing closure, and signal integrity.
- Expertise in power optimization techniques, including clock gating and multi-voltage domain design.
- Proficiency in scripting languages, such as Tcl, Python, or Perl, to enhance automation and streamline physical design tasks.
4+ years of experience in a similar role is preferred for this position.
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