Senior Design Verification Engineer
3 weeks ago
Job Title: Senior Design Verification Engineer - ASIC/SoC Verification Expert
Description:
We are seeking a highly skilled Senior Design Verification Engineer to join our team at Applied Intelligence Semiconductors Pvt Ltd. As a key member of our verification team, you will be responsible for developing and implementing verification plans, strategies, and techniques to ensure the quality and reliability of our ASIC and SoC designs.
Key Responsibilities:
- Develop testbenches using System Verilog and UVM for functional and power-aware RTL verification.
- Design and develop UVM components such as agents, scoreboards, and environments.
- Develop assertions and functional coverage to ensure comprehensive verification.
- Collaborate with cross-functional teams to identify and close gaps in functional, power-aware, and gate-level timing simulation.
- Develop C testcases for HW-FW simulation and FPGA prototyping.
- Setup and debug RTL and gate-level netlists.
- Review industry-standard specifications and augment test plans to improve verification quality.
- Participate in post-silicon bring-up, validation, and compliance testing and debug.
Requirements:
- Proven track record of verification, taking several chips from specification to tape-out.
- Proven expertise with UVM and/or System Verilog-based verification.
- Excellent understanding of ASIC verification methodologies and proven experience of verification closure.
- Experience working with source control tools, bug management tools, and release management tools such as Jenkins, Git, and Jira.
- Experience with SoC interfaces, embedded processors, networking protocols, security protocols, and video formats will be a big plus.
- Strong written and verbal communication skills and ability to work independently.
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